The invention relates to a function test evaluation apparatus for evaluating a function test of an integrated circuit in a manner that the test information is supplied to an integrated circuit to be tested and the output information outputted from the integrated circuit is compared with the expected information previously prepared.
A function test evaluation apparatus for judging if a large scale integrated circuit (LSI) such as a one-chip microcomputer is operating properly generally needs a memory (hereinafter called a local memory) for storing the expected value information and the input test information to be supplied to an integrated circuit to be tested.
FIG. 1 shows a block diagram of a conventional function test evaluation apparatus for evaluating a function test of an integrated circuit. In the figure, a control section 10 is comprised of a central processor (CPU) and a main memory 12. The main memory 12 stores the input test information for testing the function of the integrated circuit and the expected information for evaluating the response information from the integrated circuit under test. A write circuit 13 successively writes the information read out from the main memory 12 into a local memory 14.
The input test information and the expected value information having been written into the main memory 12 by the write circuit are stored in the local memory 14. The data stored in the local memory 14 is successively read out under control of an address control circuit 15 when the test is conducted. The input test information and the expected value information are supplied to an input pattern format control circuit 16 and a GO/NO GO judgment circuit 17.
In the input pattern format control circuit 16, the input test information is selected and, in the GO/NO GO judgment circuit 17, the expected value information is selected. The input test information inputted to the input pattern format control circuit 16 are time-shaped therein, are converted into necessary voltage levels by a plurality of data drivers 18.sub.1 to 18.sub.n, and are finally applied into an integrated circuit 20 to be tested. Responding to the test information, the integrated circuit 20 produces the response information which in turn are applied in parallel to a set of voltage comparators 19.sub.a1 to 19.sub.an and 19.sub.b1 to 19.sub.bn.
A reference voltage with a logical high level is further inputted to the voltage comparators 19.sub.a1 to 19.sub.an while a reference voltage with a logical low level is further applied to the voltage comparators 19.sub.b1 to 19.sub.bn. The voltage comparators 19.sub.a1 to 19.sub.an and 19.sub.b1 to 19.sub.bn are used to set the voltage level of information produced from the integrated circuit 20 to a HIGH level (logical `1`) or a LOW level (logical `0`). The information after its level is set is then applied to the GO/NO GO judgment circuit 17. The judgment circuit 17 compares the information supplied through the voltage comparators 19.sub.a1 to 19.sub.an and 19.sub.b1 to 19.sub.bn with the expected value information and evaluates the function of the integrated circuit 20 on the basis of the result of the comparison.
The operation of the function test evaluation apparatus described above will be described by using the timing charts shown in FIG. 2. First, a timing pulse TP.sub.1 as shown in FIG. 2A is supplied to the address control circuit 15. Since the control circuit 15 operates in synchronism with the timing pulse TP.sub.1, the different address information are successively inputted to the local memory 14 every period T.sub.1 of the timing pulse TP.sub.1. After a period T.sub.2 shown in FIG. 2 since the local memory 14 is addressed by the address information, the read-out operation of the information previously stored in the local memory 14 is completed. Following the read-out operation, the input pattern format control circuit 16 time-shapes the information read out in synchronism with the input timing pulse TP.sub.2 shown in FIG. 2C. Then, the information is supplied through the data drivers 18.sub.1 . . . 18.sub.n to the integrated circuit 20. The information outputted from the integrated circuit 20 is inputted to the GO/NO GO judgment circuit 17 where it is compared in synchronism with the timing TP.sub.3 with the expected value information. Since the information is read out from the local memory 14 every period T.sub.1 of the timing pulse TP.sub.1, the period T.sub.1 is the test period.
In order to evaluate the function of a LSI circuit, a great number of input test information and expected value information are necessary. Therefore, for processing the information for its evaluation within a short time, it is necessary to operate the memory at a high speed and to read out the information for a short time. Further, in order to perform the function evaluation in real time, the local memory 14 must be operated at a speed almost equal to that of the integrated circuit 20. The operation of the local memory 14 at a high speed may be realized by shortening the test period T.sub.1. However, it is impossible to make the period T.sub.1 shorter than the cycle time T.sub.2 of the local memory 14. As a consequence, in order to operate the local memory 14 at high speed, it is necessary to use a local memory with a short cycle time. However, such a local memory with a short cycle time is expensive, so that the function test evaluation apparatus is also expensive.